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S6493/s6494 series S6493 and s6494 series are si photodiode arrays efficiently combined with a signal processing circuit. the signal processing ci rcuit is formed on a single chip by the cmos process, and includes a shift register, clamp circuit, hold circuit and charge amplifier array, thus allowing a simplified external circuit configuration. the photocurrent from the photodiode array is fed to the charge amplifier connected to each element and is converted into a vol tage. the signal voltage is then sent to the clamp circuit and hold circuit, and is finally read out from the shift register in turn as a sequential video signal. the signal readout is performed by means of the charge storage method, so the output is proportional to the amount of l ight exposure (the product of incident light level and integration time). the vide output is a boxcar waveform which is low noise and easy to hand le. in addition, the readout gain can be selected from two levels by changing the voltage to the external input terminal. (the "hig h" gain is 10 times that of the "low" gain.) S6493 and s6494 series ensure easy operation since they can operate from a 5 v supply, and yet offer a maximum data rate of 250 khz. features l four types are available S6493-64: 0.8 mm pitch 64 ch S6493-128: 0.4 mm pitch 128 ch s6494-64: 1.6 mm pitch 64 ch s6494-128: 0.8 mm pitch 128 ch l simultaneous integration by using a charge amplifier array l sequential readout with a shift register l integrated clamp circuit allows low noise and wide dynamic range l two gain levels can be selected l operates from single 5 v supply input l S6493 series: long active area can be configured by use of multiple arrays phosphor screen type is also available for x-ray detection l custom designed element size and pitch available l dedicated driver circuits are available applications l image or pattern recognition system photodiode photodiode array with amplifier photodiode arrays combined with a signal processing circuit chip detail of elements kmpdc0072ea h w p photodiode diffusion area mechanical specifications parameter symbol * 1 S6493-64 S6493-128 s6494-64 s6494-128 unit element pitch p 0.8 0.4 1.6 0.8 element diffusion width w 0.6 0.25 1.3 0.6 element height h 0.8 0.4 1.6 0.8 mm number of elements - 64 128 64 128 - active area length - 51.2 102.4 mm *1: refer to following figure 1
photodiode array with amplifier S6493/s6494 series absolute maximum ratings parameter symbol value unit supply voltage vdd gain selection terminal voltage vgain clock pulse voltage v 1, v 2 start pulse voltage v st reset pulse voltage v reset hold pulse voltage v hold sample pulse voltage v sample clamp pulse voltage v clamp -0.3 to +7.0 v operating temperature * 2 topr -5 to +60 storage temperature tstg -10 to +70 c *2: no condensation recommended terminal voltage parameter symbol min. typ. max. unit supply voltage vdd 4.8 5 5.2 low gain vgain (l) vdd-0.2 vdd vdd+0.2 gain selection terminal voltage high gain vgain (h) 0 - 0.4 high level vdd-0.2 vdd vdd+0.2 clock pulse voltage low level v 1, v 2 0-0.4 high level vdd-0.2 vdd vdd+0.2 start pulse voltage low level v st 0 - 0.4 high level vdd-0.2 vdd vdd+0.2 reset pulse voltage low level v reset 0-0.4 high level vdd-0.2 vdd vdd+0.2 hold pulse voltage low level v hold 0 - 0.4 high level vdd-0.2 vdd vdd+0.2 sample pulse voltage low level v sample 0-0.4 high level vdd-0.2 vdd vdd+0.2 clamp pulse voltage low level v clamp 0 - 0.4 v electrical characteristics (ta=25 c, vdd=5 v, v 1=v 2=v reset=v hold=v clamp=v sample=5 v) S6493-64, s6494-64 S6493-128, s6494-128 parameter symbol min. typ. max. min. typ. max. unit clock pulse frequency (video data rate) f 1, f 2 15 - 250 15 - 250 khz integration time ts 0.3 - 10 0.6 - 10 ms clock pulse line capacitance c 1, c 2 -15- -30- video line capacitance cv - 20 - - 40 - pf output impedance zo - 3 - - 3 - k ? current consumption idd - 20 - - 40 - ma 2
photodiode array with amplifier S6493/s6494 series electrical and optical characteristics S6493-64 S6493-128 s6494-64 s6494-128 parameter symbol min. typ. max. min. typ. max. min. typ. max. min. typ. max. unit spectral response range 200 to 1000 200 to 1000 320 to 1000 320 to 1000 peak sensitivity wavelength p - 720 - - 720 - - 720 - - 720 - nm high gain - 0.4 4 - 0.2 2 - 0.8 8 - 0.4 4 dark output voltage * 3 low gain vd - 0.04 0.4 - 0.02 0.2 - 0.08 0.8 - 0.04 0.4 mv saturation output voltage * 3 vsat 1.3 1.6 - 1.3 1.6 - 1.3 1.6 - 1.3 1.6 - v high gain - 1.2 - - 5.8 - - 0.28 - - 1.2 - saturation exposure * 4, 5 low gain esat -12- -58- -2.8- -12- m lx s high gain - 1300 - - 270 - - 5700 - - 1300 - photo sensitivity * 5 low gain s - 130 - - 27 - - 570 - - 130 - v/ lx s photo response non-uniformity * 6 prnu - - 20 - - 20 - - 20 - - 20 % high gain - 0.2 - - 0.2 - - 0.3 - - 0.3 - noise * 7 low gain n - 0.2 - - 0.2 - - 0.2 - - 0.2 - mvrms output offset voltage * 8 vos 2.5 3 3.5 2.5 3 3.5 2.5 3 3.5 2.5 3 3.5 v [ta=25 c, vdd=5 v, v 1=v 2=v reset =v hold =v clamp =v sample=5 v, vgain=5 v (low gain), 0 v (high gain), data rate: 200 khz] *3: integration time ts=1 ms *4: saturation output voltage and exposure are determined by the upper limit of the charge amplifier. *5: measured with a 2856 k tungsten lamp. *6: when the photodiode array is exposed to uniform light which is 50 % of the saturation exposure, the photo response non- uniformity (prnu) is defined as follows: prnu = (vmax - vmin)/vaverage 100 (%) where vaverage is the average output of all elements, vmax is the output of the element that provides the maximum output, vmin is the output of the element that provides the minimum output. *7: measured at a data rate of 50 khz and integration time of 5 ms under dark condition. *8: the output offset voltage is defined as shown in following figure (output waveform of one element). output waveform of one element spectral response kmpdb0041ea driver circuit consideration the following points must be taken into account when you use a driver circuit. the input pulse must meet the pulse conditions at the input terminal. each pulse should be amplified by the buffer at a position as close to the input terminal as possible. the video output should undergo non-inverting amplification at the external readout circuit. use of a jfet input type op amp is recommended. make offset adjustment as necessary. in this case, it should be noted that the dark output level appears on the lower voltage side relative to the output offset voltage. 0.1 photo sensitivity (a/w) 190 400 600 800 1000 wavelength (nm) 0.3 0.2 (typ. ta =25 ?c) 0.4 S6493 series s6494 series 0 kmpdc0077ea dark state 120 mv typ. gnd offset voltage v os =3 v typ. saturation output voltage vsat=1.6 v typ. saturation state 3
photodiode array with amplifier S6493/s6494 series block diagram charge integration operation (1) when a reset pulse is input, all elements in the integration amplifier are reset to start integration. (2) when a hold pulse is input, output from all elements of the integration amplifier is simultaneously sent to the output hold circuit. (3) the charge integration time is equal to the time interval from the reset pulse input to the hold input. (4) when another reset pulse is input, the next integration starts. (5) the clamp and sample pulses are needed to operate the clamp circuit. readout operation (1) under the condition that complimentary clock pulse 1 and 2 are being supplied, the shift register starts operation when a st pulse is loaded. at this point, the 1 pulse must rise only once while the st is low. (2) the shift register generates an address pulse train, and the output signal accumulated in the hold circuit is read out in t urn from the first element, as a sequential signal from the video terminal. (3) the video signal is obtained as a boxcar waveform in synchronization with the positive-going edge of 2. (4) the hold pulse cannot be loaded during readout operation (shift register operation). (5) the eos (end-of-scan) signal is output in synchronization with the negative-going edge of 1 immediately before the output timing of the last element. serial readout for multistage arrangement (S6493 series) when multiple photodiode arrays are used in a serial arrangement, charge integration of each board can be performed at the same time, but the shift register of each board should be operated in sequence. the eos pulse can be used as a start pulse for the n ext stage when it is inverted. the video output terminal from all boards shoud be combined as one line via an analog switch and then connected to the external readout circuit. the analog switch should be used to select the video output only of the board being read out. recommended timing chart the operations of the S6493 and s6494 series devices can be divided into charge integration and readout operations, as follows: kmpdc0073ea kmpdc0078ea 1234 n-3 n-2 n-1 n vdd vss video eos shift resister hold circuit clamp circuit charge amplifier photodiode st 1 2 hold clamp sample reset vgain st integration time 15 s min. 1 s min. 1 2 reset hold sample clamp video eos 12345 123 n-2 n-1 n 4
photodiode array with amplifier S6493/s6494 series timing chart parameter symbol min. typ. max. unit start pulse width tpw ( st) 300 - - rise/fall time of start pulse tr ( st), tf ( st) 0 20 100 clock pulse ( 1, 2) width tpw ( 1, 2) 200 - - rise/fall time of clock pulse ( 1, 2) tr ( 1, 2), tf ( 1, 2) 0 20 100 ns hold pulse width tpw ( h) 1- -s rise/fall time of hold pulse tr ( h), tf ( h) 0 20 100 ns reset pulse width tpw ( r) 15 - - s rise/fall time of reset pulse tr ( r), tf ( r) 0 20 100 sample pulse (1) width tpw ( s1) 500 - - rise/fall time of sample pulse (1) tr ( s1), tf ( s1) 0 20 100 ns sample pulse (2) width tpw ( s2) tpw ( r) --s rise/fall time of sample pulse (2) tr ( s2), tf ( s2) 0 20 100 ns clamp pulse width tpw ( c) tpw ( r) --s rise/fall time of clamp pulse tr ( c), tf ( c) 0 20 100 sample pulse (1) - hold pulse timing t ( s1- h) 0- - hold pulse - reset pulse timing t ( h- r) 0 - - reset pulse - clamp pulse timing t ( r- c) 0- - start pulse - clock pulse ( 1, 2) timing 1 t1 ( st- 1) 0 - - start pulse - clock pulse ( 1, 2) timing 2 t2 ( st- 1) 0- - clock pulse ( 1, 2) - start pulse timing 1 t1 ( 1- st) 0 - - clock pulse ( 1, 2) - start pulse timing 2 t2 ( 1- st) 0- - ns video delay time tvd - 1 - s eos pulse delay time ted - 100 - ns kmpdc0079ea tf ( r) tf ( st) tr ( st) tpw ( st) t1 ( 1- st) tf ( 1) tr ( 2) tr ( 1) tf ( 2) tpw ( 1) tpw ( 2) t2 ( 1- st) t1 ( st- 1) t2 ( st- 1) t ( h- r) tpw ( h) tr ( h) reset 1 1 2 1 eos 90 % tvd ted video st hold sample clamp tr ( r) t ( r- c) tf ( s2) tr ( s2) tr ( s1) tpw ( s1) tr ( c) tf ( c) tpw ( c) tf ( s1) tpw ( r) tf ( h) 5
photodiode array with amplifier S6493/s6494 series a: distance from the bottom of the board to the center of the active area S6493-64: 21.15 0.2, S6493-128: 21.35 0.2 board: g10 glass epoxy connector: ps-26pe-d4lt1-pn1 (made by japan aviation electronics) a: distance from the bottom of the board to the center of the active area s6494-64: 9.35 0.2, s6494-128: 9.05 0.2 board: white ceramic window: borosilicate glass kmpda0087ea kmpda0088ea p 2.54 12 = 30.48 2.54 2.28 1.7 max. pin no. 1 2 25 26 34.02 51.2 + 0.2/-0 65.0 + 0.15/-0.15 a 10 30 10 2.54 30 4.06 6.9 6.0 6.0 ( 26) 0.64 0.05 signal processing ic chip photodiode array ( 4) 3.3 photodiode channel 1 scanning direction 1.6 + 0.2/-0.2 120 1.2 p2.54 25 = 63.5 28.25 116 102.4 photodiode channel 1 pin no. 26 pin no. 1 27 0.5 a 2 3 0.5 8.8 21 2 0.5 10 signal processing ic chip photodiode array 1.7 0.3 1.0 0.1 0.25 scanning direction dimensional outlines (unit: mm, tolerance unless otherwise noted: 0.2) S6493 series s6494 series 6
photodiode array with amplifier S6493/s6494 series pin connections S6493 series s6494 series no. symbol no. symbol 1vdd 1vss 2 vdd 2 vdd 3vss 3vdd 4 nc 4 vdd 5 video 5 vss 6 vss 6 video 7nc 7vss 8 1 8 1 9nc 9vdd 10 nc 10 vss 11 vdd 11 eos 12 vss 12 1 13 eos 13 2 14 1 14 vdd 15 2 15 st 16 vdd 16 vss 17 st 17 1 18 vss 18 hold 19 1 19 1 20 hold 20 clamp 21 1 21 clamp 22 reset 23 sample 23 vgain 24 reset 24 vdd 25 vgain 25 vdd 26 vss 26 vss precautions for use (1) the signal processing circuit chips of the S6493 and s6494 series are protected against static electricity. however, in ord er to prevent possible damage to the chip, implement electrostatic countermeasures such as grounding of the operator, work tabl e and tools. furthermore, the devices must be protected against surge voltages from external equipment. (2) S6493 series since the photodiode array chip is not protected, handle it carefully so it will not become contaminated or scratched.pho to- diode array performance may deteriorate if operated at high temperatures and humidity, so the housing should be designed to be airtight. the signal processing circuit chip and its wire bonding are covered with a resin coating for protection, but never touch these portions. in addition, take care when installing the board so that it does not warp. (3) s6494 series if the input window becomes dirty or scratched, the output uniformity may deteriorate. avoid touching the window with bar e hands. cleaning the window surface before use with cloth, cotton swab or paper moistened with ethyl alcohol is advised. wiping the window with dry cloth may generate static electricity and therefore should be avoided. pin assignment symbol assignment description vdd supply voltage voltage input vss ground st start pulse negative-going pulse input 1 clock pulse 1 pulse input 2 clock pulse 2 pulse input 1 reset reset pulse negative-going pulse input hold hold pulse positive-going pulse input sample sample pulse negative-going pulse input clamp clamp pulse positive-going pulse input vgain gain selection terminal voltage voltage input vdd : low gain setting vss : high gain setting video video output positive-going output from positive potential, boxcar waveform eos end of scan positive-going pulse output 7
c6785 , c6495 the c6785 and c6495 are driver circuits specifically designed for use with hamamatsu photodiode arrays with amplifier. (the c67 85 is for the S6493 series and the c6495 is for the s6494 series.) both the c6785 and c6495 include a signal generator that provides timing p ulses used to drive the sensor and a signal processing circuit that performs video signal amplification and dc restoration. the signal inputs required are start pulse (start), clock pulse (clk) and +5 v. features l ideally suited for use with a photodiode array with amplifier c6785: for S6493 series c6495: for s6494 series l simple operation (with start pulse, clock pulse and +5 v) l can be installed on the reverse side of a photodiode array with amplifier l compact size l gain of a photodiode array with amplifier is selectable from pc board applications l operation of a photodiode array with amplifier amplifier driver circuit for photodiode array with amplifier drive a photodiode array with amplifier by simple signal inputs absolute maximum ratings parameter symbol value unit supply voltage vd 7 v operating temperature topr 50 c storage temperature tstg 60 c electrical characteristics parameter symbol min. typ. max. unit supply voltage (for digital circuit) vd 4.9 5 5.5 v vst (h) 3.5 - - start pulse (start) voltage vst (l) - - 1.5 v start pulse width tpw-st 1/f-clk - - s start pulse rise/fall time tr-st, tf-st - - 500 ns vclk (h) 3.5 - - clock pulse (clk) voltage vclk (l) - - 1.5 v clock pulse frequency f-clk 30 - 500 khz clock pulse width tpw-clk 30 - - ns input clock pulse rise/fall time tr-c, tf-c - - 500 ns vtrig (h) 4.5 5 5.5 trigger pulse (trigger) voltage vtrig (l) 0 - 0.8 v trigger pulse rise /fall time tr-tri, tf-tri - - 500 ns output data video data rate dvrate- 100 250 khz 8
driver circuit for photodiode array with amplifier c6785, c6495 kaccc0056ea kaccc0057ea timing controller cf-sel a.gnd video video gnd clk start trigger x2.5 S6493 series ch.1 ch.n end +5 v sw1 eos j1 j2 +5 v connector cable a.gnd video +5 v gnd clk start trigger x2.5 s6494 series ch.1 ch.n timing controller end +5 v cf-sel sw1 eos video block diagram c6785 c6495 9
driver circuit for photodiode array with amplifier c6785, c6495 pin connections j1, cn1: 5483-08ax (made by molex) pin no. signal input/output description 1 clk input hcmos compatible pulse for synchronizing the circuit and sensor 2 start input hcmos compatible positive logic pulse for initializing the circuit 3 trigger output hcmos compatible positive logic pulse for a/d conversion 4 eos output hcmos compatible negative logic pulse used as end-of-scan signal 5 +5 v input supply voltage: +5 v max. 70 ma 6 gnd - circuit ground 7 video output video signal output positive-going pulse 8 a.gnd - circuit ground used to ground the coaxial line of video a connector 5480-08 that mates with the 5483-08ax connector is supplied with the c6785 and c6495. j2: xg4c-2634 (made by omron) pin no. signal input/output description 1 vdd output sensor: supply voltage for cmos ic 2 vdd output sensor: supply voltage for cmos ic 3 vss output sensor ground 4 nc - no connection 5 video input sensor video signal output 6 vss output sensor ground 7 nc - no connection 8 1 output sensor: clock pulse for shift register scan, hcmos compatible 9 nc - no connection 10 nc - no connection 11 vdd output sensor: supply voltage for cmos ic 12 vss output sensor ground 13 eos input sensor: end-of-scan signal 14 1 output sensor: clock pulse for shift register scan, hcmos compatible 15 2 output output sensor: clock pulse for shift register scan, hcmos compatible 16 vdd output output sensor: supply voltage for cmos ic 17 st output output sensor: video signal output start pulse, hcmos compatible 18 vss - sensor ground 19 1 output sensor: clock pulse for shift register scan, hcmos compatible 20 hold output sensor: charge amplifier output hold signal, hcmos compatible 21 1 output sensor: clock pulse for shift register scan, hcmos compatible 22 clamp output sensor: charge amplifier output clamp signal, hcmos compatible 23 sample output hcmos compatible, positive logic pulse for initializing the circuit 24 reset output sensor: charge amplifier output reset signal, hcmos compatible 25 vgain output sensor gain switching: h=gain low, l=gain high 26 vss - sensor ground a connector xg4m-2630-t that mates with the xg4c-2634 connector is supplied with the c6785 and c6495. 10
driver circuit for photodiode array with amplifier c6785, c6495 cn2: xr2c (made by omron) pin no. signal input/output description 1 vss - sensor ground 2 vdd output sensor: supply voltage for cmos ic 3 vdd output sensor: supply voltage for cmos ic 4 vdd output sensor: supply voltage for cmos ic 5 vss - sensor ground 6 video input sensor video signal output 7 vss - sensor ground 8 1 output sensor: clock pulse for shift register scan 9 vdd output sensor: supply voltage for cmos ic 10 vss - sensor ground 11 eos input sensor: end-of-scan signal 12 1 output sensor: clock pulse for shift register scan 13 2 output sensor: clock pulse for shift register scan 14 vdd output sensor: supply voltage for cmos ic 15 st output sensor: shift register scan start pulse 16 vss - sensor ground 17 1 output sensor: clock pulse for shift register scan 18 hold output sensor: charge amplifier output hold signal 19 1 output sensor: clock pulse for shift register scan 20 clamp output sensor: charge amplifier output clamp signal 21 sample output sensor: charge amplifier output sample signal 22 reset output sensor: charge amplifier output reset signal 23 vgain output sensor gain switching: h=gain low, l=gain high 24 vdd output sensor: supply voltage for cmos ic 25 vpd output reverse voltage for photodiode array 26 vss - sensor ground pulse timing kaccc0058ea clk start (sample) (hold) (clamp) (reset) ( st) ( 1) ( 2) trigger eos video 1 23 4 n n-1 pixel number note: ( ) is internal signal 2 s min. 11
driver circuit for photodiode array with amplifier c6785, c6495 hamamatsu photonics k.k., solid state division 1126-1 ichino-cho, hamamatsu city, 435-8558 japan, telephone: (81) 053-434-3311, fax: (81) 053-434-5184, http://www.hamamatsu.c om u.s.a.: hamamatsu corporation: 360 foothill road, p.o.box 6910, bridgewater, n.j. 08807-0910, u.s.a., telephone: (1) 908-231-0 960, fax: (1) 908-231-1218 germany: hamamatsu photonics deutschland gmbh: arzbergerstr. 10, d-82211 herrsching am ammersee, germany, telephone: (49) 08152 -3750, fax: (49) 08152-2658 france: hamamatsu photonics france s.a.r.l.: 8, rue du saule trapu, parc du moulin de massy, 91882 massy cedex, france, telepho ne: 33-(1) 69 53 71 00, fax: 33-(1) 69 53 71 10 united kingdom: hamamatsu photonics uk limited: 2 howard court, 10 tewin road, welwyn garden city, hertfordshire al7 1bw, unit ed kingdom, telephone: (44) 1707-294888, fax: (44) 1707-325777 north europe: hamamatsu photonics norden ab: smidesv ? gen 12, se-171 41 solna, sweden, telephone: (46) 8-509-031-00, fax: (46) 8-509-031-01 italy: hamamatsu photonics italia s.r.l.: strada della moia, 1/e, 20020 arese, (milano), italy, telephone: (39) 02-935-81-733, fax: (39) 02-935-81-741 information furnished by hamamatsu is believed to be reliable. however, no responsibility is assumed for possible inaccuracies or omissions. specifications are subject to change without notice. no patent rights are granted to any of the circuits described herein. ?200 1 hamamatsu photonics k.k. cat. no. kmpd1020e03 jun. 2001 dn kacca0048ea kacca0049ea 45.0 5.0 70.0 72.6 40.0 50.0 (4 ) 3.3 8.6 1.6 sw1 sw2 j2 j1 connector j2 pin no.26 pin no.2 pin no.8 pin no.1 connector j1 no.1 no.25 component side cn1: 5483-08ax (molex) cn2: xr2c (omron) attached to sensor side 4.4 83.0 76.0 pin no. 1 pin no. 26 pin no.1 pin no.8 cn1 sw1 p2.54 25 25.0 18.0 2.0 1.6 6.8 8.3 6.9 min. (with the 5480-08 mating connector inserted) 4- 3.3 s6494 series dimensional outlines (unit: mm, tolerance unless otherwise noted: 0.2) c6785 c6495 12

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